Sequential pulse generator employing first and second delay means controlling pulse duration and spacing, respectively



Dec. 22, 1964 H. MOGENSEN 3,162,315

SEQUENTIAL PULSE GENERATOR EMPLOYING FIRST AND SECOND DELAY MEANS CONTROLLING PULSE DURATION AND SPACING, RESPECT IVELY Filed Nov. 2 1961 4 Sheets-Sheet 1 fig/(2.1? .16. 557.10. 1 5 .1d'. 5,316.

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SEQUENTIAL PULSE GENERATOR EMPLOYING FIRST AND SECOND DELAY MEANS CONTROLLING PULSE DURATION AND SPACING, RESPECTIVELY Filed Nov. 2 1961 4 Sheets-Sheet 3 4 W l A i INVENTOR. f/Azer Mow/v55 Arron/Er Dec. 22, 1964 H MQGENSEN 3,162,815

SEQUENTIAL PULSE GENERATOR EMPLOYING FIRST AND SECOND DELAY MEANS CONTROLLING PULSE DURATION AND SPACING, RESPECTIVELY Filed Nov. 2 1961 4 Sheets-Sheet 4 -i x L- INVENTOR. M) Ma GEA/Sf/V Arron/ r United States Patent F SEQUENTIAL PULSE GENERATOR EMPLOY ING FIRST AND SECOND DELAY MEANS CONTROLLING PULSE URATION AND SPACING, RESPECTIVELY Harry Mogensen, Levittowu, N.J., assignor to Radio Corporation of America, a corporation of Delaware Filed Nov. 2, 1961, Ser. No. 149,732 13 Claims. (Cl. 32862) This invention relates to pulse generators. The invention is useful in digital data processing ssyterns although it is not restricted to this use.

The object of the invention is to provide a circuit which produces pulses which are all of the same, precise duration and. which are spaced from one another the same or different time intervals.

The circuit of the invention includes a plurality of flipflops and input gates to the flip-flops for producing control pulses which set and reset the flip-flops. A first delay means common to all of the gates controls the duration of all pulses. A second delay means common to all of the gates or a second and one or more other delay means controls the spacing between pulses. v

The invention is described in greater detailbelow and is illustrated in the following drawing of which:

FIGS. la-le are diagrams to explain the symbols employed in FIG. 2;

FIG. 2 is a block circuit diagram of a form of the present invention in which the spacing between pulses is the same;

FIG. 3 is a drawing of waveforms present at various places in the circuit of FIG. 2;

FIG. 4 is a block circuit diagram of a form of the invention in which" the spacing between pulses can be different; and

FIG. 5 is a drawing of waveforms present at various places in the circuit of FIG. 4.

Similar reference letters are used in the various figures. Elements in FIG. 4 which are similar to corre sponding elements in FIG. 2 carry the samereference numerals plus 100 as the elements in FIG. 2.

A number of blocks shown in the figures represent known circuits. The circuits of the blocks are actuated by electrical signals applied to the blocks. When a signal is at one level, it represents the binary digit one and when it is at another level, such-as zero volts, it represents the binary digit zero. For the sake of the discussion which follows, it may be assumed that a high level signal represents the binary digit one and a low level signal the binary digit zero. Also, to simplify the discussion, rather than speaking of an electrical signal being applied to a block or logic stage, it is sometimes stated that a one or a zero is applied to a block or logic stage.

Throughout the figures capital letters are used to represent signals indicative of binarydigits. For example, A may represent the binary digit zero or'the binary digit one. X represents the complement of A. In some casesyletters are employed in Boolean equations as a convenient means for describing the circuit operation.

A number of elementary logic circuits are present in FIGS. 2 and 4. The symbols which are employed in FIGS. 2 and 4 and, in some cases, their Boolean equations, are shown in FIGS. la through 16. For example, FIG. la illustrates a nor gate which is also sometimes known as a none gate. This gate may consist of an and gate which has an inverter in series with each of its input leads. Alternatively, it may-consist of an or gate followed by an inverter. There may be two or more inputs to the gate. Regardless of the way ,in'which the reset terminal of all fliplops.

nor gate is implemented, its Boolean equations (for the two input case) are the ones shown in FIG. la.

The convention adopted for a flip-flop is somewhat different than that usually employed, When the flip-flop is set, it produces a one output at its 0 output terminal and a zero output at its 1 output terminal. When the flip-flop is reset, it produces a one output at its 1 out put terminal and a zero output at its 0 output terminal. This is shown in FIG. 1d.

One form of the invention is shown in FIG. 2. The circuit includes flip-flops 10, 12, 14 and 16, input nor gates 18-28 for setting and resetting flip-flops 10, 12 and 14, and input or gates 30 and 32 for setting and resetting flip-fiop 16. The 0 output of flip-flop 16 is applied through an inverter 34 and delay line 36 to a second inverter 38. The output of inverter 38 is applied through a third inverter 40 and delay line 42 to a fourth inverter 44. The output of the second inverter 38 is also applied to a fifth inverter 46. The output of inverter 44 is applied as one input to nor gates 24, 26 and 28 and is alsoapplied through a sixth inverter 47 as an input to nor gates 18, 20 and 22.

The various flip-flop outputs are fed back in different ways as inputs to the nor gates. For example, the B output of flip-flop 12 and E' output of flip-flop 14 serve as inputs to nor gate 18. The outputs of the nor gates are the control pulses. As there are six such gates, the system produces six pulses in time sequences. These are legended C through C The control pulses C C and C are applied as inputs to or gate 30 (upper right of figure). The control pulses C C and C serve as inputs to or gate 32.-

It will be shown shortly that the delay line 36 controls the duration of pulses C -C This delay line may be fixed or controllable, as shown. It will also be shown that the delay line 42 controls the spacing between pulses. This delay line also may be fixed or controllable.

In the discussion which follows of the operation of the circuit of FIG. 2, both FIGS. 2 and 3 should be referred to. It may be assumed that initially all of the flip-flops are reset. The reset means is not shown in the figure, however, it may include a pulse generator in the program area of the computer which is connected to the Thereset flip-flops produce outputs K, E, E and F all equal to zero. The H input to nor gate 26 isinitially a one so that this gate is inactivated. All other gates are also disabled.

In order to start the pulse generator, H is changed from one to zero. This occurs at time t When H changes to zero, all of the inputs to nor gate 26, namely i', K, P, R and H are Zero and this nor" gate therefore conducts and producesa C =l pulse. The C pulse sets flip-flop 14. The C pulse is also applied through or gate 30 to the set terminal of flip-flop 16 and sets this flop-flop.

When flip-flop 16 is set, F changes to one. This signal is inverted by inverter 34 and the resulting zero signal is delayed an interval X by delay line 36. The delayed zero signal is inverted by inverter 33 and appears as a signal P=l at lead 48. The P signal is one of the inputs to nor gate 26. Accordingly, when it changes to one, nor gate 26 is disabled and C changes to zero.

From the foregoing description it is clear that the duration of pulse C is substantially equal to the delay inserted by delay line 36. Accordingly, this delay line, if varied, varies the pulse duration.

The P=l signal is applied'through inverter 40 to delay line 42. The-delayed signal is applied to inverter 44 and appears as a delayed one signal at lead 50. The one minating pulse C trolled the duration of pulse C it is clear that the pulses signal is inverted by inverter 47 and appears as a Til edge of pulse C is equal to the delay Y inserted by delay a means 42. Here and in the case of delay means 36, the delays inserted by the inverters and other stages are ignored since they are relatively small compared to the delays inserted by the delay lines and, like the delays inserted by the delay lines, remain fairly constant. 7 control of the delay inserted by delay means 42 is therefore a suitable means for controlling the spacing between the pulses C and C V p During the time control pulseC is generated, a R=l signal is applied to nor gates 24, 26-and 28 inactivating these gates. Similarly, a 17:1 signaliis applied to nor gates 18 and 20 inactivating these gates. Thus, the only gate which is enabled is nor gate 22. It can be shown that in any casein which one of the nor gates is enabled, all other nor gates are disabled.

The control pulse C serves as'an input-to or gate 32. The pulse C therefore resets flip-flop 16 changing F to zero. After the delay inserted by delay line 36, F changes from zero to one disabling gate 22 and ter- Since the delay line 36 also con C and C are of precisely the same duration, It can be shown that the delay line 36 also controls the duration of pulses C -C and therefore six pulses, C -C are of the same duration.

After the delay inserted by delay means 42, R changes to zero. R serves as one of-the inputs to nor gate 28. All other inputs to this nor gate, namely P, K and Bare all zero. Control pulse C previously set flip-flop 12 changing B from one to zero. Therefore, nor gate 28 is enabled and produces the pulse C As in the previous case, the spacing between the lagging edge of pulse C and the leading edge of pulse C is determined by delay line 42. Accordingly, the spacing between pulses C and C is precisely the same as that between pulses C and C It can be shown that the same condition holds for the remaining pulses and that therefore the spacing between each succeeding pulse is preciselythe sarne.

From the discussion above and from the drawing of W3Vf0fn1S"Qf FIG. 3, it can readily be seen how the remaining pulses C C and C are generated.

The circuit of F16 4 is, in many respects, similar to the one of FIG. 2. However, the circuit of FIG. 41includes, in addition to all of the elements of the circuit of FIG. 2, inverters 68, 62, and 54 and a delay means 70. The latter introduces a delay Z which may be fixed or of controllable duration. Moreover, rather than being a delay line, element 7.0 may be an asynchronous stage which produces an'output signal at lead'56 after an interval dependent on the time required by the stage to perform its function. As one example, element 70 may be an asynchronous adder. I

One further difference between the circuit of FIG. 4 and the one of FIG. 2 is that the permutations of input signals to the nor gates is somewhat different in the circuit of FIG. 4 than in the circuit of FIG. 2'. Also, some of the inputs to the nor gates are now the Q and ('25 signals which are not available in the circuit of FIG. 2.

In the discussion which follows of the operation of the circuit of FIG. 4, both FIGS. 4 and 5 should be referred to. As in the case of the circuit of FIG. 2, all of the fiip flops in the circuit of FIG. 4 are initially reset. When H, the pulse generator start signal, is changed from one to zero, all of the inputs to nor gate 126 are zero. The nor gate therefore conductsand produces a'C =l pulse. The C pulse sets flip-flop 114. The C pulse is also applied through or gate 130 to the set terminal of flip-flop 116 and sets this flip-flop.

When flip-flop 116 is set, F changes to one. This signal is inverted, by inverter 134 and the resulting zero signal is delayed an interval X by delay line 136. The

delayed zero signal is inverted by inverter 138 and appears as a signal P=1 atlead 148. The P signal is one ofthe inputs to nor. gate 126.- Accordingly, when it changes to one, nor gate 126 isdisabled and C changes to zero. Thus, the duration of pulse C is'substantiallyequal to the delay X inserted by delay means 136. 1

The P: 1- signal is applied through inventor 140, delay means 142, and inverter 144 to lead 58. Thus, an R=l signal appears on lead 58 an interval Y alter the signal P=l appears. The R=l signal is applied [through inverter 68, delay means 70, inverter 62 and inverter 54 to lead 60. Accordingly, an interval Z after the signal R=1 appears, a signal 11:0 appears.

The signal Q=0 is one of the inputs to nor gate 122. All of the other inputs to this gate are also zero. Accordingly, this gate conducts and produces the C =1 comtmol pulse. It is clear firom the foregoing description that the interval between the lagging edge of control pulse C and the leading edgeof control pulsec is the interval The durationot' each pulse, regardless of the be- Qtween pulses, is the same, namely X.

It should be appreciated that other spacings between pulses are possible with different permutations of inputs toithe norv gates. lit should also be appreciated that although; in the pulse group illustnaited, the spacing between pulses is first longer, then shorter, and then longer, other combinations of spacings are possible. Further, although in the embodiment illustrated only two delay means 142 and 70 are employed for controlling the spacing between pulses, additional delay means may be used to obtain additional permutations of pulse spacing inteiyals.

The circuits of. FIGS. 2 and 4 produce six control pulses. It should be appreciated, however, that the invention is not limited to one which produces only six pulses. For example, if the number of flip-flops is increased from four'to five, and the number of input nor gates are increased to eight, eight control pulses can be 1 produced. Other similarcircuits can be designed for producing many more than eight or fewer than six pulses. The circuits of FIGS. 2 and 4e1'nploy nor gates. The circuit can use instead other types of logic gates as, for example, and gates, providedthe proper permutations of the-input signals to these gates are chosen. 2

What is claimed is: i r 1. In a circuit for generating a plurality of spaced pulses, each appearing on a separate output line; a first delay meanstcoupled to all'of said lines, for controlling I the pulse duration; and a second delay means coupled to all of saidlines for controlling the spacing between pulses. V 2. In a circuit for generating a plurality of spaced pulses, each appearing on a separate output line;

first means, including a delay means having a delay Al coupled to all of said lines for terminating each pulse an interval substantially equal to Al after each pulse starts; and 1 l l second means, including a second delay means haying.

a delay M coupled to all of said lines for starting Y-l-Z, that is, the delays by delay means 142 and 30 70 I p 7 v each pulse an interval substantially equal to M after the termination of the previous pulse.

3. A pulse generator comprising,

a plurality of flip-flop stages;

input gates to the flip-flop stages for producing control pulses for setting and resetting the flip-flop stages;

a first delay means coupled to all of said gates for making each pulse of the same duration;

and a second delay means coupled to all of said gates .for making the spacing between pulses of the same duration.

4. A pulse generator comprising,

a plurality of flip-flop stages which produce output signals at two diiferent levels when set, and which produce output signals of complementary value when reset;

input gates to the flip-flop stages responsive to different permutations of the flip-flop output signals for producing control pulses for setting and resetting the flip-flop stages;

a first delay means responsive to said control pulses and coupled to all of said gates for producing an output which controls the duration of each pulse; and v a second delay means responsive to the output of the first delay means and coupled to all of said gates for controlling the spacing between said pulses.

5. A pulse generator comprising, in combination,

a plurality of flip-flops each having a set terminal and a reset terminal, and each having terminals at which output signals are produced; 1

a plurality of input gates for the flip-flops, at least one connected to each set terminal of a flip-flop, and at least one connected to each reset terminal of a flipfl p;

connections from the flip-flop output terminals to the input gates for applying difierent permutations of signals to the gates for conditioning the gates to conduct in a selected order;

a first delay means coupled to all gates and responsive to an output produced by a gate, when enabled, for applying a disabling signal to the gate after a predetermined interval of time; and

a second delay means coupled to all gates for applying enabling signals to the gates conditioned to conduct, each a predetermined interval of time after the previously enabled gate is disabled.

6. A pulse generator comprising, in combination,

a plurality of flip-flops each having a set terminal and a reset terminal, and each having terminals at which output signals are produced;

a plurality of input nor gates for the flipflops, at

least one connected to each set terminal of a flipflop, and at least one connected to each reset terminal of a flip-flop;

connections from the flip-flop output terminals to the luput gates for applying different permutations of slgnals to the gates for conditioning the gates to conduct in a selected order;

a first delay means coupled to all gates and responsive to an output produced by a gate, when enabled, for applying a disabling signal to the gate after a predetermined interval of time; and

a second delay means coupled to all gates and responsive to the disabling signal produced by the first delay means for applying enabling signals to the gates conditioned to conduct, each a predetermined in- 6 connected to each set terminal of a flip-flop, and at least one connected to each reset terminal of a flipp;

connections from the flip-flop output terminals to the input gates for applying difierent permutations of signals to thegates for conditioning the gates to conduct in a selected order;

a first delay means coupled to all gates and responsive to the output produced by a gate, when enabled, for applying a disabling signal to the gate after a predetermined interval of time; and

a second delay means responsive to the disabling signal produced by the first delay means for enabling the next gate conditioned to conduct, after a predetermined interval of time.

8. In a circuit for generating a plurality of spaced pulses, each appearing on a separate output line;

a first delay means coupled to all of said lines, for

producing disabling signals for controlling the duration of each pulse; and v a plurality of other delay means connected to the first delay means for producing respective outputs delayed successively greater time intervals from the time at which the disabling signal is produced for controlling the spacing between successive pulses.

9. A pulse generator comprising, in combination,

a plurality of flip-flops, each having a set terminal and a reset terminal, and each having output terminals;

a plurality of input gates for the flip-flops, at least one connected to each set terminal of a flip-flop, and at least one connected to each reset terminal of a pp;

connections from the flip-flop output terminals to the input gates for applying diiferent permutations of signals to the gates for conditioning the gates to conduct in a selected order;

a first delay means coupled to all gates and responsive to the output produced by a gate, when enabled, for applying a disabling signal to the gate after a predetermined interval of time;

a second delay means coupled to some of said gates and responsive to said disabling signal for applying enabling signals to said gates at a time At after a disabling signal occurs; and

a third delay means coupled to some of said gates and responsive to a delayed disabling signal for applying an enabling signal to said gates a time M and At after a disabling signal occurs.

10. A pulse generator comprising, in combination,

(a) a plurality of logic gates;

(b) a first delay means coupled to all gates for producing a disabling signal an interval At after any one of the gates is enabled;

(0) a second delay means coupled to the first delay means for producing an enabling signal an interval At after the disabling signal occurs; and

(d) circuit means coupled to the first and second delay means for disabling the enabled gate in response to the disabling signal and enabling another gate in response to the enabling signal. 11. A pulse generator comprising, in combination, (a) a plurality of logic gates;

(b) means coupled to one gate for enabling the same,

whereby the gate produces an output;

(c) a first delay means coupled to all gates for producing a disabling signal an interval At after any one of the gates is enabled;

(d) a second delay means coupled to the first delay means for producing an enabling signal an interval At after each disabling signal occurs; and

(e) circuit means coupled to the first and second delay means for disabling the enabled gate in response to the disabling signal, thereby terminating said output, and enabling another gate in response to the 7 enabling signal, thereby causing said other gate to produce an output. V 12. A pulse generator comprising, in combination,

:(a) a plurality of logic gates, one of which is enabled means and responsive to the respective disabling signals for producing enabling signals, each an interval At; after a disabling signal occurs; and

- (d) circuit means coupledto the first and second delay means for disabling each enabled gate at a time At after that gate is enabled, in response to each disabling signal, and for enabling the other gates, in a given order, each an interval A2 after disabling signalv occurs. 1

13. A pulse generator comprising, in combination,

(a) a plurality of logic gates, one of which is enabled and produces an output; a

(b) a first delay means coupled through OR gate means and a flip-flop to all gates and responsive to the respective outputs thereofiior producing disabling signals, each an interval At; after a gate produces an P r (c) a second delay means coupled to thefirst delay means and responsive to the respectivedisabling signals for producing enabling signals, each an interval m 'af ter a disabling signal occurs; and

(d) circuit means coupled to the first and second delay means for disabling each enabled gate at a time At, after that gate is enabled, in response to eachdisabling signal, and for-enabling the othertgat'es, in a given order, each an interval A13 after disablingsignal occurs. a i t 7 References. Cited in the file of this patent:

' UNITED STATES PATENTS Harmon j nug; 21, 1962 

1. IN A CIRCUIT FOR GENERATING A PLURALITY OF SPACED PULSES, EACH APPEARING ON A SEPARATE OUTPUT LINE; A FIRST DELAY MEANS COUPLED TO ALL OF SAID LINES, FOR CONTROLLING THE PULSE DURATION; AND A SECOND DELAY MEANS COUPLED TO ALL OF SAID LINES FOR CONTROLLING THE SPACING BETWEEN PULSES. 